1. Field of the Invention
This invention relates to the field of memory circuitry. More particularly, this invention relates to the control and configuration of sense amplifiers for use in sensing differential voltages between bit lines when reading data from an array of bit cells within memory circuitry.
2. Description of the Prior Art
It is known to provide memory circuitry comprising an array of bit cells within which columns of bit cells are connected by bit line pairs. The bit line pairs are precharged to a given voltage and then one of the bit lines of the pair is discharged depending upon the contents of the bit cell within a column that is being read. The difference in voltage which arises between the bit lines of the bit line pair as a result of this discharge is sensed by sense amplifier circuitry coupled to the bit lines.
A performance parameter that is desirable to improve for a memory is the speed with which data can be read therefrom. One factor limiting this speed is the amount of time needed for a sense amplifier to sense the voltage difference which arises between bit lines when being read in accordance with the above. Furthermore, a problem with sense amplifier circuitry as devices become smaller is that mismatches between the circuit elements in the sense amplifier circuitry can give rise to failure or poor performance. In particular, sense amplifiers may contain a pair of inverters which are cross-coupled. If the inverters are not well matched, then they may be switched incorrectly, or switched more slowly, by the voltage difference arising between the bit lines in the expected manner. One way of dealing with this is to make the circuit elements including at least the inverters larger than would otherwise be necessary so that mismatches can be reduced. However, making the inverters larger than is necessary is disadvantageous from an area and circuit density point of view.